A novel 30 nm self-aligned bottom-gate MOSFET with edged source/drain-tie

Author

Chen-Chi Tsai ; Jyi-Tsong Lin ; Yi-Chuen Eng ; Po-Hsieh Lin

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

This paper presents a non-classical architecture called the self-aligned bottom-gate MOSFET with edged source/drain-tie (SAESDTBG). According to the 2-D numerical simulation, the proposed structure can decrease source/drain (S/D) resistance that increases on state current (I_on). Also, it can achieve device characteristic comparable to traditional bottom-gate (TBG) MOSFET and can effectively reduce the self-heating effect (SHE), resulting in improved thermal stability. It can reduce 36.4% lattice temperature of channel and increase 19.2% electron velocity compared with TBG MOSFET because of our S/D-tie scheme.

Keywords

MOSFET; electric resistance; thermal stability; 2D numerical simulation; S/D resistance; S/D-tie scheme; SAESDTBG; SHE; TBG MOSFET; device characteristic; edged source/drain-tie; electron velocity; lattice temperature; nonclassical architecture; self-aligned bottom-gate MOSFET; self-heating effect; size 30 nm; source/drain resistance; state current; thermal stability; Immune system; Lattices; Logic gates; MOSFET circuits; Stability analysis; Temperature; Thermal stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467616

Filename

6467616