Complete Modeling of Large Via Constellations in Multilayer Printed Circuit Boards

This paper presents, for the first time, the comprehensive modeling of complete via constellations consisting of several thousands of vias in multilayer printed circuit boards using the physics-based approach. For each computational step of the physics-based approach, several alternatives are analyzed with regard to their computational efficiency, and calculation times are discussed as a function of the number of simulated vias. The results of this analysis are used in combination with previous studies to determine an efficient yet accurate algorithm for the simulation of large numbers of vias. The impact of the stackup configuration on the computational effort of the algorithm is analyzed, and the most computationally expensive parts of the calculation process are identified. A parallelization of the algorithms is carried out to accelerate the critical calculation tasks. As an evaluation example, simulation results for a via array consisting of 10 000 vias and eight cavities are shown. With the proposed simulation methods, the computation time for this via array is about 6.5 h per frequency point on a single CPU and about 40 min per frequency point with the parallel version running on 16 CPUs.