Very fast pipelined RSA architecture based on Montgomery´s algorithm

This paper present a design of RSA-encryption using Pipelined radix-2 Montgomery´s architecture. The architecture design exploits the algorithm to achieve high speed and efficient computation. The design separates the computation of Montgomery modular multiplication into different clock cycles to achieve high frequency clock. This design supports input from 1 to 14 block data and efficient in the number of total logic element and register. The design has been successfully verified whether functional Verilog RTL simulation, FPGA timing simulation and run in Signal Tap FPGA simulation. The design occupies logic elements 1157, 1030 registers, and able to run up to 261.85 MHz on Altera Cyclone II EP2C35 F672C6. The proposed design has been successfully synthesized using Synopsys with CMOS 0.18mu technology. The area is 63567.5 mum2 and the delay is 3.35 ns.