DocumentCode
3415974
Title
Design considerations for a 2 MHz synchronous buck converter in CMOS
Author
Fukui, Atsuo ; Knight, Jonathan
Author_Institution
Nat. Semicond. Japan, Ltd., Tokyo, Japan
fYear
2004
fDate
24-27 May 2004
Firstpage
71
Lastpage
74
Abstract
The design considerations for a 2 MHz synchronous buck converter for a cellular phone RF power amplifier supply are presented. Particular emphasis is placed on the problems associated with achieving this high switching frequency with a current-mode architecture and in an inexpensive 0.5 μm CMOS process.
Keywords
CMOS integrated circuits; DC-DC power convertors; PWM power convertors; current-mode circuits; switching convertors; 0.5 micron; 0.6 V; 2 MHz; 5.5 V; CMOS converter; cellular phone RF power amplifier supply; current-mode architecture; high switching frequency; internally-compensated PWM control loop; synchronous buck converter; CMOS integrated circuits; DC-DC power conversion; Pulse width modulated power converters;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on
Print_ISBN
4-88686-060-5
Type
conf
DOI
10.1109/ISPSD.2004.1332860
Filename
1332860
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