Noise Isolation Modeling and Experimental Validation of Power Distribution Network in Chip-Package

Author

Park, Hyunjeong ; Yoon, Changwook ; Koo, Kyoungchoul ; Kim, Joungho

Author_Institution

Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

2007

fDate

9-13 July 2007

Firstpage

1

Lastpage

6

Abstract

This paper models the chip and the package power distribution network in the simplified SPICE-level. The model is successfully validated by experiments using Vector Network Analyzer. By using the SPICE-level model, the noise isolation between the noise current source at the chip and the power distribution network at the package is analyzed from 1 MHz to 3 GHz. The contribution of each part in the power distribution network is also analyzed by experiments. The transfer impedances are simulated and measured the power distribution network between the chip and the package varying with the wire- bond and the on-package decoupling capacitor, case by case.

Keywords

SPICE; electronics packaging; power supplies to apparatus; SPICE-level model; frequency 1 MHz to 3 GHz; noise current source; noise isolation modeling; on-package decoupling capacitor; power distribution network; transfer impedances; vector network analyzer; Capacitors; Electromagnetic interference; Impedance measurement; Noise generators; Packaging; Power measurement; Power systems; Radio frequency; Resonance; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-1349-4

Electronic_ISBN

1-4244-1350-8

Type

conf

DOI

10.1109/ISEMC.2007.57

Filename

4305637