An electronic parallel neural CAM for decoding

Author

Alspector, Joshua ; Jayakumar, Anthony ; Ngo, Bon

Author_Institution

Bellcore, Morristown, NJ, USA

fYear

1992

fDate

31 Aug-2 Sep 1992

Firstpage

581

Lastpage

587

Abstract

The authors report measurements taken on an electronic neural system configured for content addressable memory (CAM) using a high-capacity architecture. It is shown that Boltzmann and mean-field learning networks can be implemented in a parallel, analog VLSI system. This system was used to perform experiments with mean-field CAM. The hardware settles on a stored codeword in about 10 μs roughly independent of code length. The capacity is far higher than that of the standard Hopfield architecture

Keywords

Boltzmann machines; VLSI; content-addressable storage; decoding; learning systems; neural chips; parallel architectures; Boltzmann learning networks; content addressable memory; decoding; electronic parallel neural CAM; high-capacity architecture; mean-field CAM; mean-field learning networks; parallel analogue VLSI system; Annealing; CADCAM; Computer aided manufacturing; Decoding; Hardware; Neurons; Noise generators; Signal processing; Temperature distribution; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks for Signal Processing [1992] II., Proceedings of the 1992 IEEE-SP Workshop

Conference_Location

Helsingoer

Print_ISBN

0-7803-0557-4

Type

conf

DOI

10.1109/NNSP.1992.253654

Filename

253654

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3416191