Serial and interleaved architectures for computing real FFT

The Fast Fourier transform (FFT) is an important operation in digital signal processing applications. In applications such as biomedical signal processing, the signals are real. The real-valued signals exhibit conjugate symmetry, giving rise to redundant values in the outputs. This property can be exploited to reduce arithmetic computations, area and power consumption. This paper presents hardware architectures for computing real FFT that exploits this conjugate symmetry property where the inputs are processed in a serial manner. This is facilitated by pushing the twiddle factor values across various butterfly stages. In this paper, two different serial FFT architectures are presented: one using real and the other using hybrid datapaths. These architectures process one sample per clock cycle and are well suited for low-sample-rate applications such as biomedical. These architectures are also modified so that two independent computations can be interleaved in the same datapath. The advantage of interleaving is reduction in area, and is attractive for applications where FFT computation of two independent real signals is required.