DocumentCode :
3416408
Title :
Modeling and synthesis of communication subsystems for loop accelerator pipelines
Author :
Dutta, Hritam ; Hannig, Frank ; Schmid, Moritz ; Keinert, Joachim
Author_Institution :
Univ. of Erlangen-Nuremberg, Erlangen, Germany
fYear :
2010
fDate :
7-9 July 2010
Firstpage :
125
Lastpage :
132
Abstract :
The communication synthesis for data transfer and synchronization between loop accelerators is a major challenge in streaming applications. The complexity of the problem arises from the fact that optimal memory mapping and address generation in communication subsystems for parallel data access and out-of-order communication depend on tiling and scheduling choices. This paper solves the problem of communication synthesis by leveraging the windowed synchronous data flow (WSDF) model for communication synthesis. In this context, an intermediate representation of communicating loops in the polyhedral model and a unified methodology for their projection onto the WSDF model is proposed. Finally, we present the architecture template, synthesis methodology, and overhead of the communication primitive.
Keywords :
Central Processing Unit; Communication system control; Computational modeling; Context modeling; Hardware; Integrated circuit synthesis; Kernel; Out of order; Parallel processing; Pipelines;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-specific Systems Architectures and Processors (ASAP), 2010 21st IEEE International Conference on
Conference_Location :
Rennes, France
ISSN :
2160-0511
Print_ISBN :
978-1-4244-6966-6
Electronic_ISBN :
2160-0511
Type :
conf
DOI :
10.1109/ASAP.2010.5540760
Filename :
5540760
Link To Document :
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