Electrical performance of top-gate amorphous silicon thin-film transistors

In this paper, we have studied the electrical performance of a top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT). This type of TFT has an I_ON/I_OFF ratio of about 10⁶ for the drain-source voltage Vds=10 V. Its threshold voltage V_T is about 2V. Using the current-voltage characteristics of TFTs with different channel lengths, we extract the intrinsic field-effect mobility of about 0.23 cm^{/Vsec. We also find that the specific contact resistance of this top-gate TFT is about 17 Ω-cm2, which is still too high for the applications in the TFT liquid crystal display (TFT-LCD). Channel conduction activation energy, which is deduced from the TFT I-V characteristics at different temperature, is about 0.18 eV when the transistor is in ON-state. For the bottom-gate TFT, the ON-state activation energy is about 0.12 eV. The estimated interface state density, obtained by field-effect (FE) method, is about 1012 cm-2 eV-1, which is about one order of magnitude higher than that obtained for the bottom-gate TFT. We have found that bias-temperature-stress (BTS) induced shift in threshold voltage (ΔV_T) follows closely the stretched-exponential stress time dependence. A stretched-exponential exponent β extracted at 80°C for the top-gate TFT is slightly larger than the one for the bottom-gate TFT. The subthreshold behavior of the top-gate TFT is observed to degrade significantly under large positive bias stress condition, which indicates the trapping of negative charges or/and creation of negative defect states}