• DocumentCode
    3416460
  • Title

    A graph-theoretic approach to clock skew optimization

  • Author

    Deokar, Rahul B. ; Sapatnekar, Sachin S.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
  • Volume
    1
  • fYear
    1994
  • fDate
    30 May-2 Jun 1994
  • Firstpage
    407
  • Abstract
    This paper addresses the problem of minimizing the clock period of a circuit by optimizing the clock skews. We incorporate uncertainty factors and present a formulation that ensures that the optimization will be safe. In a paper by J.P. Fishburn (see IEEE Trans. on Computers, vol. 39, no. 7, p. 945-951, 1990) the problem of clock period optimization is formulated as a linear program. We first propose an efficient graph-based solution that takes advantage of the structure of the problem. We also show that the results obtained by Fishburn may result in exceedingly large skews, and propose a method to reduce these skews without sacrificing the optimality of the clock period. Experimental results on several ISCAS89 benchmark circuits are provided
  • Keywords
    graph theory; linear programming; logic design; minimisation; sequential circuits; timing; ISCAS89 benchmark circuits; clock period minimisation; clock skew optimization; graph-theoretic approach; uncertainty factors; Clocks; Delay effects; Flip-flops; Integrated circuit interconnections; Latches; Polynomials; Resource management; Safety; Uncertainty; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
  • Conference_Location
    London
  • Print_ISBN
    0-7803-1915-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1994.408825
  • Filename
    408825