Experimental study on deformation potential at MOS interf

Summary form only given. We propose a new physical model for deformation potential (D_ac) at MOS interface. In the proposed model, D_ac increases sharply near Si/SiO2 interfaces. D_ac in SOI FETs with SOI thickness (T_SOI) ranging from 4 to 60 nm is evaluated from Shubnikov-de Haas (SdH) oscillations. It is demonstrated, for the first time, that D_ac is increased sharply at the MOS interface within a range of few nanometers; whereas in traditional modeling constant D_ac of greater than bulk Si value has been assumed. Since SOI has two Si/SiO2 interfaces, D_ac effectively increases in extremely-thin SOI (ETSOI). The increase of D_ac is more evident at 300 K or under positive substrate bias (V_b) because electrons are distributed in entire ETSOI and are affected by both the interfaces. The increased D_ac results in μ_e degradation in ETSOI; whereas it contributes to an increase in stress-induced μ_e enhancement in thinner T_SOI devices. This finding is indispensable for designing high-performance and/or low-power 3D FETs including FinFETs, ETSOI FETs, and nanowire FETs, because these FETs have more MOS interface per unit volume.