Modeling of leakage current distributions in series connected polysilicon thin film transistors

Leakage current is an important parameter in thin film transistors (TFTs) for achieving gray scales in active matrix liquid crystal displays (AMLCDs). Leakage regulation is especially important in polysilicon TFTs, where the leakage is significantly greater than in their amorphous silicon counterparts. To reduce the leakage current, it is a common practice to place two polysilicon TFTs in series, which may reduce the leakage current by over an order of magnitude. In this work, it is shown how leakage current in a series connected pair can be analytically predicted from the I-V characteristics of a single FET for the first time, and how the leakage current distribution of single transistors may affect the distribution of the series connected devices. These implications are important for estimating the pixel yield in AMLCDs from single device characteristics