64-point fast efficient FFT architecture using Radix-23 single path delay feedback

Here we present a new design of a 64-point fast Fourier transform circuit. The design is derived from Radix-2³ algorithm and implemented using single path delay feedback architecture. This approach ensures high memory and multiplier utilizations. The 64-point FFT is realized by decomposing into two-dimensional structure of 8-point FFTs. Each of this FFT is re-decomposed into 4-point and 2-point FFTs. This decomposition reduces the number of non-trivial twiddle factor into just one. Thus we only need one complex multiplier for the design. The complex multiplier is realized using modified Booth (radix-4) encoding algorithm to achieve faster computational speed. The validity and efficiency of the proposed circuit has been thoroughly verified by functional simulation, timing simulation, and FPGA implementation. The proposed design has been successfully synthesized using Synopsys with TSMC 0.18mu technology. The core area is 0.47 mm2. The power consumption is 29.7 mW. The time delay is 6 ns. The circuit computes one serial-to-serial data in 116 clock cycles. Thus our design has 3 advantages: small area, low power consumption, and fast computation.