K-band CMOS frequency doubler with high fundamental rejection

Author

Sen Wang ; Chun-Tuan Chang

Author_Institution

Dept. of Electron. Eng., Nat. Taipei Univ. of Technol., Taipei, Taiwan

Volume

50

Issue

17

fYear

2014

fDate

Aug. 14 2014

Firstpage

1211

Lastpage

1212

Abstract

The design of a frequency doubler with current-reuse and fundamental rejection topology is presented. The frequency doubler is fabricated by a standard 0.18 μm CMOS process with a chip size of 0.57 mm². The DC power consumption is 13.9 mW. In addition, the measured conversion gain is between -4.4 and -d5.24 dB from 10 to 12 GHz input frequency. With the proposed active notch filter in the cascode stage of the doubler, a superior fundamental rejection is obtained. The measured fundamental rejection is between 32.4 and 53.8 dB.

Keywords

CMOS integrated circuits; active filters; cascade networks; frequency multipliers; integrated circuit design; microwave frequency convertors; microwave integrated circuits; notch filters; power consumption; CMOS process; DC power consumption; K-band CMOS frequency doubler; active notch filter; cascode stage; conversion gain; current-reuse; frequency 10 GHz to 12 GHz; fundamental rejection topology; gain -4.4 dB to -5.24 dB; power 13.9 mW; size 0.18 mum; size 0.57 mm;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2014.0480

Filename

6880216