Surface Laminar Circuit (TM) carrier and flip chip assembly enabling technologies for advanced computer applications

The current semiconductor industry association (SLA) roadmap shows that by the year 2000, chips with sizes up to 400 mm² and chip pad counts (for package interconnection) will approach 2600 bumps. These requirements are necessary in order to keep up with continuing demand for faster on-chip clock rates and faster access to CACHE memory. IBM has been practising Flip Chip (FC) Controlled Collapse Chip Connection (C4) to ceramic substrates for over 30 years. Over the past 10 years IBM has developed a low cost printed wiring board (PWB) alternative, Surface Laminar Circuit (TM). This technology combined with FC, will allow IBM to meet the SIA requirements. This work presents an advanced MCM-L test vehicle (TV) that makes use of both Surface Laminar Circuit (TM) and FC to demonstrate feasibility of interconnecting 20×20 mm large chips and C4 bump counts up to 2400. This work focuses on the design of the carrier, some of the assembly challenges encountered and selected reliability results