Title :
Partition, Packing and Clock Distribution: A New Paradigm of Physical Design
Author :
Kajitani, Y. ; Takahashi, A. ; Nakatake, S. ; Azegami, K.R.
Keywords :
Algorithm design and analysis; Clocks; Delay; Design automation; Graph theory; Integrated circuit interconnections; Large scale integration; Registers; Timing; Very large scale integration;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812577
