DocumentCode :
3416980
Title :
Partition, Packing and Clock Distribution: A New Paradigm of Physical Design
Author :
Kajitani, Y. ; Takahashi, A. ; Nakatake, S. ; Azegami, K.R.
fYear :
2000
fDate :
2000
Firstpage :
11
Lastpage :
11
Keywords :
Algorithm design and analysis; Clocks; Delay; Design automation; Graph theory; Integrated circuit interconnections; Large scale integration; Registers; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-0487-6
Type :
conf
DOI :
10.1109/ICVD.2000.812577
Filename :
812577
Link To Document :
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