DocumentCode :
3417094
Title :
“Second level assembly of chip scale, Chip-on-Flex packages”
Author :
Fillion, R.A. ; Shaddock, D.M. ; Burdick, W.E. ; Kapadia, H.
Author_Institution :
Corp. Res. & Dev., Gen. Electr. Co., Schenectady, NY, USA
fYear :
1997
fDate :
2-4 Apr 1997
Firstpage :
104
Lastpage :
108
Abstract :
The Chip-on-Flex (COF) technology was developed as a low cost multichip module (MCM) technology for application in few chip circuit designs. The COF process mounts bare chips, active side down, onto a pre-fabricated flex circuit and electrically connects the bare chips to the flex using a direct metallurgical process. The chips are encapsulated using a standard plastic molding process to complete the MCM. Single chip versions of the COF technology have been implemented as Chip Scale Packages (CSP), to address those applications not suited to MCM approaches and/or to satisfy the packaging needs for the companies that are reluctant to commit to any MCM technology, at this time. This paper addresses CSP issues and approaches, the COF CSP process and structure, and the assembly issues related to CTE solder fatigue, pad metal thickness requirements and underfilling
Keywords :
assembling; multichip modules; packaging; COF technology; CTE solder fatigue; chip scale package; chip-on-flex package; encapsulation; flex circuit; metallurgical process; multichip module; pad metal thickness; plastic molding; second level assembly; underfilling; Assembly; Bonding; Chip scale packaging; Costs; Flexible electronics; Integrated circuit interconnections; Integrated circuit technology; Multichip modules; Nonhomogeneous media; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multichip Modules, 1997., International Conference on
Conference_Location :
Denver, CO
Print_ISBN :
0-7803-3787-5
Type :
conf
DOI :
10.1109/ICMCM.1997.581156
Filename :
581156
Link To Document :
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