Scalable fabrication of high performance graphene FETs with self-aligned buried gates

Author

Yanjie Wang ; Bo-Chao Huang ; Ming Zhang ; Congqin Miao ; Ya-Hong Xie ; Woo, J.C.S.

Author_Institution

Dept. of Electr. Eng., Univ. of California, Los Angeles, Los Angeles, CA, USA

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents a scalable technique to fabricate high performance graphene transistors with self-aligned buried gates process. Graphene FETs with two different structures have been compared and the buried gated structure shows less fringing capacitance and more reliable contacts. The buried-gate graphene transistor shows field-effect mobility of 6,100 cm²/V·s according to the transconductance measurement. This result paves the way for manufacturable high quality graphene transistor technology.

Keywords

field effect transistors; graphene; semiconductor device manufacture; C; buried gated structure; buried-gate graphene transistor; field-effect mobility; fringing capacitance; high performance graphene FET; high performance graphene transistors; manufacturable high quality graphene transistor technology; scalable fabrication; self-aligned buried gates; transconductance measurement; Capacitance; Contact resistance; FETs; Graphene; Logic gates; Metals; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467684

Filename

6467684