High speed digital hybrid PLL frequency synthesizer

The conventional PLL (phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this problem. It operates in high speed, but the hardware complexity and power consumption are another serious problems since the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit makes the negligible overshoot and much shorter settling time for the ultra fast switching speed. Also, the hardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL.