DVB-T synchronizer architecture design and implementation

This paper presents the design of synchronizer hardware for DVB-T receiver. The main function of synchronizer is to detect and compensate the time offset and frequency offset which happen during transmission as well as frame start detection. Proposed synchronizer utilizes cyclic prefix of OFDM signals. The design includes computational bit precision modeling, architecture design, register-transfer-level (RTL) codes implementation, and final synthesis into FPGA. The synthesis result shows that the synchronizer can satisfy the required specification of at least more than 40 MHz clock speed, i.e., specifically 55 MHz clock setup.