Title :
Status condition analysis during data path verification of sequential circuits
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
A control path-data path partition based sequential circuit verification scheme can avoid the state explosion problem. Of the two broad tasks involved in data path verification namely, register transfer operation analysis and status condition analysis, the second one is described. The issues addressed are (i) time expended in status detection and (ii) completeness of the analysis function. A status analyzer, based on a simplifying assumption, has been presented
Keywords :
circuit analysis computing; formal verification; integrated logic circuits; logic CAD; sequential circuits; control path-data path partition; data path verification; register transfer operation analysis; sequential circuits; status analyzer; status condition analysis; status detection time; Computer languages; Computer science; Data analysis; Detectors; Explosions; Impedance; Integrated circuit interconnections; Memory; Registers; Sequential circuits;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812587
