Design of a lower-error fixed-width multiplier for speech processing application

A lower-error and lower-variance n×n multiplier is suitably proposed for VLSI design. Considering the next lower significant stage in P_n-1 column and a useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of the Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for a speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors