Title :
A methodology for the placement and optimization of decoupling capacitors for gigahertz systems [CMOS VLSI]
Author :
Choi, J. ; Chun, S. ; Na, N. ; Swaminathan, M. ; Smith, L.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper discusses a method for computing the effect of decoupling capacitors on the power delivery system for gigahertz packages and boards. A fast and accurate computational method is presented that can be used to estimate the amount of decoupling required, the type of capacitor to be used and its location (on-chip, package or board)
Keywords :
CMOS integrated circuits; VLSI; capacitors; circuit optimisation; integrated circuit design; integrated circuit packaging; CMOS; VLSI; computational method; decoupling capacitors; gigahertz systems; packages; power delivery system; Capacitors; Circuit noise; Clocks; Frequency; Impedance; Optimization methods; Packaging; Power engineering computing; Semiconductor device noise; Voltage;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812602
