Title :
Cost trade-offs in system on chip designs
Author :
Khare, J. ; Heineken, H.T. ; d´Abreu, M.
Author_Institution :
DFM/DFT Group, Level One Commun., Sacrameto, CA, USA
Abstract :
Advances in technology have led to a drive towards system on chip (SoC) designs. However manufacturing and test costs have increased as rapidly as design complexity. Hence, in order to produce SoC designs at reasonable cost, both system-level and die-level cost trade-offs must be made. This paper illustrates the methodologies used in analyzing such trade-offs. Examples in the paper indicate that using advanced technologies to manufacture SoC designs may sometimes be detrimental in terms of total system costs
Keywords :
VLSI; integrated circuit design; integrated circuit economics; integrated circuit testing; SoC designs; cost trade-offs; design complexity; die-level cost trade-offs; system on chip designs; system-level cost trade-offs; test costs; total system costs; Costs; Design for manufacture; Design for testability; Graphics; Logic; Manufacturing; Packaging; Radio frequency; Random access memory; System-on-a-chip;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812606
