Designing FIR filters with enhanced Fermat ALUs

Author

Shahkarami, M. ; Jullie, G.A. ; Miller, W.C.

Author_Institution

Windsor Univ., Ont., Canada

Volume

3

fYear

1999

fDate

36342

Firstpage

287

Abstract

This paper presents architectures for implementing general purpose FIR arrays, using enhanced Fermat ALU theory. The structure is based on a direct product finite polynomial ring mapping (MRRNS) of a redundant binary representation of the input data; in effect we exploit a double redundancy of the input representation and the mapped polynomial representation. By exploiting this redundancy, with attendant reductions in coefficient growth due to polynomial multiplication, we are able to considerably reduce the probability of overflow error

Keywords

CMOS digital integrated circuits; FIR filters; VLSI; arrays; digital arithmetic; digital filters; digital signal processing chips; error analysis; filtering theory; integrated circuit design; polynomials; redundancy; 0.35 micron; 0.5 micron; CMOS DSP chip; FIR filter design; direct product finite polynomial ring mapping; double redundancy; enhanced Fermat ALUs; filter architectures; general purpose FIR arrays; input representation; mapped polynomial representation; overflow error probability reduction; polynomial multiplication; redundant binary representation; Cathode ray tubes; Clocks; Dynamic range; Fault tolerance; Finite impulse response filter; Optical wavelength conversion; Polynomials; Redundancy; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.778841

Filename

778841