DocumentCode
3417479
Title
Maximizing wafer productivity through layout optimizations
Author
Ouyang, C. ; Heineken, H.T. ; Khare, J. ; Shaikh, S. ; d´Abreu, M.
Author_Institution
Level One Commun., Sacramento, CA, USA
fYear
2000
fDate
2000
Firstpage
192
Lastpage
197
Abstract
Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and has been shown to lower die cost by 4.6%. This paper applies DFM to the routing. In particular this paper analyzes the effects of various routing options on wafer productivity and shows that if properly applied DFM can lead to a further die cost reduction of 9%
Keywords
VLSI; cellular arrays; circuit layout CAD; circuit optimisation; design for manufacture; integrated circuit layout; network routing; DFM; design for manufacturability; die costs; layout optimizations; routing; standard cell libraries; wafer productivity; Circuit faults; Conducting materials; Fabrication; Frequency; Insulation; Integrated circuit modeling; Lead; Productivity; Semiconductivity; Semiconductor materials;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location
Calcutta
ISSN
1063-9667
Print_ISBN
0-7695-0487-6
Type
conf
DOI
10.1109/ICVD.2000.812608
Filename
812608
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