Title :
A 600V HVIC process with a built-in EPROM which enables new concept gate driving
Author :
Shimizu, K. ; Rittaku, S. ; Moritani, J.
Author_Institution :
Power Device Works, Mitsubishi Electr. Corp., Fukuoka, Japan
Abstract :
A junction isolation type 600 V HVIC process, which can produce EPROM memory devices, is developed for the first time. In this process, the 0.8 μm CMOS design rule is applied and it is 20% finer than previous work. A new concept gate driver can be realized with a digital trimming circuit, in which dead-time control is possible. The trial fabrication devices exhibit compatible characteristics for the 0.8 μm CMOS and EPROM. The modified-MFFP (multiple floating field plate) structure with GSR (ground-coupled shield ring) is applied to 600 V Nch/PchMOSs for level shift circuits, and as a result of reduction of the influence of the electric field from the level shift wiring, each device exhibits a high breakdown voltage beyond 700 V.
Keywords :
CMOS integrated circuits; EPROM; driver circuits; power integrated circuits; semiconductor device breakdown; 0.8 micron; 600 V; 700 V; CMOS; MFFP structure; Nch/PchMOS; breakdown voltage; built-in EPROM; dead-time control; digital trimming circuit; gate drive circuit; ground-coupled shield ring; junction isolation HVIC process; level shift circuits; multiple floating field plate structure; CMOS integrated circuits; Driver circuits; EPROM; Power integrated circuits;
Conference_Titel :
Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on
Print_ISBN :
4-88686-060-5
DOI :
10.1109/ISPSD.2004.1332951
