Breaking the scaling barrier of large area lateral power devices: an 1mΩ flip-chip power MOSFET with ultra low gate charge

The conduction performance of low-voltage lateral power semiconductor devices deteriorates considerably with increasing device size due to the parasitic resistance of metal interconnects, commonly known as the "scaling limitation". In this paper, we introduce an innovative concept to overcome the problem by integrating a unique metal interconnect scheme with chip-scale packaging. We have designed and fabricated a sub-10 V class power MOSFET with a record-low R_DSON of 1 mΩ at a gate voltage of 6 V, or 1.25 mΩ at a gate voltage of 4.5 V, approximately 50% of the lowest R_DSON previously reported. The new device has a total gate charge Q_g of 22 nC at 4.5 V and a performance figure of merit of less than 30 mΩ-nC. This represents a 3× improvement over the state of the art trench MOSFETs. The new MOSEFT technology can be used to enable next-generation, multi-MHz, high-density DC/DC converters for future CPU cores and many other high-performance power management applications.