Title :
Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations
Author :
Ma, Jun ; Parhi, Keshab K. ; Deprettere, Ed F.
Author_Institution :
Minnesota Univ., Minneapolis, MN, USA
Abstract :
CORDIC based cascade orthogonal IIR digital filters have sharp transition band and exhibit low sensitivity in both the pass band and stop band which are suitable for VLSI implementations. However, the achievable sample rate of these filters is limited due to the presence of feedback loops. To overcome the speed limitation and achieve high-speed/low-power implementations, a novel algorithm transformation technique is proposed based on retiming and orthogonal matrix decomposition techniques which can increase the maximum filter sample rate to 𝒪(1) level which is independent of the filter order. The proposed parallel and pipelined architectures consist of only Givens rotations which can be mapped onto CORDIC arithmetic based processors
Keywords :
IIR filters; VLSI; cascade networks; digital filters; digital signal processing chips; filtering theory; high-speed integrated circuits; low-power electronics; matrix decomposition; parallel architectures; pipeline processing; timing; CORDIC arithmetic based processors; CORDIC based IIR digital filters; Givens rotations; VLSI implementation; algorithm transformations; cascade orthogonal IIR digital filters; feedback loops; high-speed operation; low-power implementation; maximum filter sample rate; orthogonal matrix decomposition techniques; parallel orthogonal filter architectures; pipelined orthogonal filter architectures; retiming; Band pass filters; Digital filters; Feedback loop; Filtering theory; IIR filters; Matrix decomposition; Pipeline processing; Polynomials; Transfer functions; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.778856
