Title :
Topological routing amidst polygonal obstacles
Author :
Bhunia, Swarup ; Sur-Kolay, Susmita
Author_Institution :
Delsoft India Pvt. Ltd., Calcutta
Abstract :
This paper presents a fast graph-traversal based greedy approach for solving the problem of topological routing in the presence of polygonal obstacles. The polygonal obstacles represent pre-routed nets or groups of circuit blocks. Routing paths for all the nets are constructed incrementally and concurrently. Design rules for separation are modeled as constraints on edges and vertices. The experimental results obtained are very encouraging
Keywords :
VLSI; circuit layout CAD; graph theory; integrated circuit layout; network routing; network topology; VLSI layout; circuit blocks; fast graph-traversal based greedy approach; polygonal obstacles; pre-routed nets; topological routing; Art; Circuit synthesis; Joining processes; Linear programming; Pins; Polynomials; Probes; Routing; Testing; Very large scale integration;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812621
