DocumentCode
3417698
Title
A novel CMOS down-conversion mixer with current reuse technique
Author
Myoung, No Gil ; Choi, Byoung Gun ; Park, Seong Su ; Park, Chul Soon
Author_Institution
Sch. of Eng., Inf. & Commun. Univ., Daejeon, South Korea
Volume
5
fYear
2005
fDate
4-7 Dec. 2005
Abstract
A novel low voltage and power mixer topology for 5GHz wireless LAN applications is presented in this paper. To reduce power dissipation, a novel mixer topology with a low supply voltage and using the current reuse technique is designed using a 0.18 μm CMOS process. The designed down-conversion mixer has a conversion gain of 7.5dB, a P1dB of -16Bm and an IIP3 of -6dBm, respectively, with LO power of -7dBm while consuming 1.6mA under a 1.5V supply voltage. The chip size including pads is 0.77mm × 0.81mm.
Keywords
CMOS analogue integrated circuits; MMIC mixers; integrated circuit design; low-power electronics; network topology; 0.18 micron; 1.5 V; 1.6 mA; 5 GHz; 7.5 dB; CMOS down-conversion mixer; current reuse technique; low power mixer toplogy; low supply voltage; low voltage mixer topology; power dissipation reduction; wireless LAN applications; Baseband; CMOS technology; Circuit topology; IEEE members; Low voltage; MOS devices; Power dissipation; RF signals; Radio frequency; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings
Print_ISBN
0-7803-9433-X
Type
conf
DOI
10.1109/APMC.2005.1607094
Filename
1607094
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