DocumentCode
3417760
Title
Design for strong testability of RTL data paths to provide complete fault efficiency
Author
Wada, Hiroki ; Masuzawa, Toshimitsu ; Saluja, Kewal K. ; Fujiwara, Hideo
Author_Institution
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Ikoma, Japan
fYear
2000
fDate
2000
Firstpage
300
Lastpage
305
Abstract
In this paper, we propose a DFT method for RTL data paths to achieve 100% fault efficiency. The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The DFT method requires lower hardware overhead and shorter test generation time than the full scan method, and also improves test application time drastically compared with the full scan method
Keywords
VLSI; automatic test pattern generation; data flow graphs; design for testability; fault diagnosis; high level synthesis; logic testing; VLSI; combinational ATPG tool; complete fault efficiency; design for strong testability; hierarchical test; lower hardware overhead; register transfer level data paths; shorter test generation time; stuck-at faults; test application time; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Design for testability; Design methodology; Hardware; Iron; Latches; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location
Calcutta
ISSN
1063-9667
Print_ISBN
0-7695-0487-6
Type
conf
DOI
10.1109/ICVD.2000.812625
Filename
812625
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