DocumentCode
3418534
Title
Predicate Elimination Technique in Binary Translation for IA-64 Architecture
Author
Song, Zong-Yu ; Su, Ming
Author_Institution
Nat. Digital Switching Syst. Eng. &Technol. R&D Center, Zhengzhou
fYear
2006
fDate
Nov. 29 2006-Dec. 1 2006
Firstpage
209
Lastpage
212
Abstract
EPIC (explicitly parallel instruction computing) architectures, such as the Intel IA-64 (Itanium), support novel features such as explicit instruction-level parallelism and predicated instructions. While these features promise to make code more efficient, the fact that these new architectural features means that EPIC code is more difficult to analyze than code for more traditional architectures. This paper describes a technique for removing predication instructions from optimized binary programs in a way that is guaranteed to preserve program semantics, and thereby improve the quality of binary translation for IA-64.
Keywords
optimising compilers; parallel architectures; parallelising compilers; program diagnostics; EPIC code analysis; Intel IA-64 architecture; explicitly parallel instruction computing architecture; instruction-level parallelism; optimized binary program translation; predicated instruction elimination technique; program semantics; Computer aided instruction; Computer architecture; Concurrent computing; Emulation; Logic; Optimizing compilers; Parallel processing; Research and development; Switching systems; Systems engineering and theory;
fLanguage
English
Publisher
ieee
Conference_Titel
Artificial Reality and Telexistence--Workshops, 2006. ICAT '06. 16th International Conference on
Conference_Location
Hangzhou
Print_ISBN
0-7695-2754-X
Type
conf
DOI
10.1109/ICAT.2006.99
Filename
4089241
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