A study of process/device/layout co-design for full-chip ESD protection in BCD technology

Author

Rui Zhu ; Fei Yao ; Shijun Wang ; Wang, Aiping ; Liji Wu ; Xiangmin Zhang ; Baoyong Chi

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A study of process-device-layout co-design procedure for full-chip electrostatic discharge (ESD) protection design for high-voltage (HV) ICs in a Bipolar-CMOS-DMOS (BCD) technology is reported. The full-chip ESD protection scheme includes I/O and power clamp ESD protection. Co-design using mixed-mode TCAD ESD simulation technique ensures design optimization and prediction. Test result confirms full-chip ESD protection of at least 4.5K V.

Keywords

CMOS integrated circuits; bipolar integrated circuits; electrostatic discharge; integrated circuit layout; technology CAD (electronics); BCD technology; bipolar-CMOS-DMOS technology; design optimization; full-chip ESD protection; full-chip electrostatic discharge protection design; high-voltage IC; mixed-mode TCAD ESD simulation; power clamp ESD protection; process-device-layout codesign procedure; Clamps; Electrostatic discharges; Integrated circuit modeling; Surge protection; Surges; Testing; Thyristors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467756

Filename

6467756