DocumentCode
3418588
Title
Implicit vs. explicit resource allocation in SMT processors
Author
Cazorla, Francisco J. ; Knijnenburg, Peter M W ; Sakellariou, Rizos ; Fernandez, Enrique ; Ramirez, Alex ; Valero, Mateo
Author_Institution
DAC, UPC, Barcelona, Spain
fYear
2004
fDate
31 Aug.-3 Sept. 2004
Firstpage
44
Lastpage
51
Abstract
In a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe different resource sharing models in SMT processors. We show that explicit resource allocation can improve SMT performance. In addition, it enables SMTs to solve other QoS requirements, not realizable before.
Keywords
microprocessor chips; multi-threading; parallel architectures; quality of service; resource allocation; SMT processors; explicit resource allocation; implicit resource allocation; quality of service; resource sharing model; simultaneous multithreaded architecture; Costs; Degradation; Hardware; Microprocessors; Processor scheduling; Registers; Resource management; Surface-mount technology; Throughput; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Print_ISBN
0-7695-2203-3
Type
conf
DOI
10.1109/DSD.2004.1333257
Filename
1333257
Link To Document