DocumentCode :
3419006
Title :
Analysis and hardware design of a scalable dual JPEG-2000 entropy coder
Author :
Aouadi, I. ; Hammami, O.
Author_Institution :
ENSTA, Paris, France
fYear :
2004
fDate :
31 Aug.-3 Sept. 2004
Firstpage :
227
Lastpage :
233
Abstract :
The JPEG-2000 image compression standard is increasingly gaining widespread importance. The rich variety of features makes it highly suitable for a large spectrum of applications but at the same time its associated complexity makes it hard to optimize for particular implementations. One the key step during the processing is entropy coding which takes about 70% of the execution time. We propose in this paper an analysis and hardware design of a dual entropy coder with the goal of being used as a coprocessor to the general JPEG-2000 flow.
Keywords :
data compression; entropy codes; field programmable gate arrays; hardware-software codesign; image coding; logic design; JPEG-2000; co-processors; dual entropy coder; hardware design; image compression standard; Arithmetic; Code standards; Entropy; Hardware; IEC standards; ISO standards; Image coding; Propagation losses; Satellites; Wavelet transforms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Print_ISBN :
0-7695-2203-3
Type :
conf
DOI :
10.1109/DSD.2004.1333281
Filename :
1333281
Link To Document :
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