DocumentCode
3419019
Title
Planar inductors with subdivided conductors for reducing eddy current effects
Author
Peter, M. ; Hein, H. ; Oehler, F. ; Baureis, P.
fYear
2003
fDate
11-11 April 2003
Firstpage
104
Lastpage
106
Abstract
In this work, a method for reducing eddy current effects in planar inductors is presented. This patent pending method has already been demonstrated to be effective for microstrip lines. In this work we present measurements that demonstrate that the maximum quality factor of a planar inductor in a standard 0.35 /spl mu/m CMOS process with three metal layers could be improved by up to 35% to a value of 8.0.
Keywords
CMOS integrated circuits; Q-factor; conductors (electric); eddy currents; inductors; radiofrequency integrated circuits; 0.35 micron; CMOS RFIC; eddy current; planar inductor; quality factor; subdivided conductor; CMOS process; Conductors; Eddy currents; Inductors; Magnetic fields; Measurement standards; Q factor; Scattering parameters; Silicon; Spirals;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Monolithic Integrated Circuits in RF Systems, 2003. Digest of Papers. 2003 Topical Meeting on
Conference_Location
Grainau, Germany
Print_ISBN
0-7803-7787-7
Type
conf
DOI
10.1109/SMIC.2003.1196680
Filename
1196680
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