Implementation of Automatic Gain Control in OFDM digital receiver on FPGA

An appropriate design based on well-defined system parameters and architecture can make a huge difference in the performance. In particular, there is a need for improved digital Automatic Gain Control (AGC) for use in Orthogonal Frequency Division Multiplexing (OFDM) system. In this paper, we study the principle of the AGC loop, and adopt an appropriate AGC loop model which takes hardware resource and performance in considering. On this basis, we give a detail on how to design parts of AGC loop on FPGA, including implementation process and setting parameters. The performances of the locking time and gain jitter are given in theory. Then the achieving results on FPGA is shown to improve the design is feasible and effective.