A 3.65 mW 5 bit 2GS/s flash ADC with built-in reference voltage in 65nm CMOS process

Author

Jiale Yang ; Yong Chen ; He Qian ; Yan Wang ; Ruifeng Yue

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A low power 5 bit 2 GS/s flash ADC is designed for 60 GHz wireless communication system using 65 nm CMOS process. The proposed ADC is implemented by calibrated comparators array with built-in reference voltage instead of resistor reference ladder, which will reduce the power consumption. Simulation results show that, the ADC obtains ENOB of 4.99 bit at low input frequency and 4.72 bit at Nyquist bandwidth, consuming 3.65 mW with a 1.2 V supply voltage, achieving a low FoM value of 57 fJ/conversion step.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit design; ladder networks; millimetre wave integrated circuits; resistors; CMOS process; ENOB; Nyquist bandwidth; built-in reference voltage; calibrated comparators array; flash ADC; frequency 60 GHz; low input frequency; power 3.65 mW; power consumption; resistor reference ladder; storage capacity 4.72 bit; storage capacity 4.99 bit; storage capacity 5 bit; voltage 1.2 V; wireless communication system; Arrays; Calibration; Clocks; MOS capacitors; Power demand; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467783

Filename

6467783