Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c

In this paper, a 512-point, 2.7 GS/s fast Fourier transform (FFT) processor embedded with mixed-radix multi-path delay-feedback (MRMDF) structure is proposed. To meet the high throughput requirement of IEEE 802.15.3c (WPANs), the architecture of eight parallel data-paths is adopted. Considering the hardware complexity and high performance, 512 point FFT computation is decomposed into radix-2⁵ and radix-2³ so that the number of the multiplications is reduced by 30% comparing with the traditional method. Furthermore, the complex multipliers are also optimized and replaced by a set of constant multipliers. The proposed FFT processor has been implemented using FPGA, and the result shows that the throughput rate (T.R.) up to 2.7GS/s@338MHz can be achieved.