Pipeline-level control of self-resetting pipelines

In this paper, we present a synchronization approach to support data flow in clockless designs using single-rail encoding. This approach is based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset phase when its output is , and an evaluate phase when its output is the result of the evaluation of its inputs. To insure correct operation, data flow from one stage to another when the preceding stage is in the evaluate phase while the following stage is in the reset phase. To support this data flow, a latch-based synchronization mechanism is proposed. This mechanism yields an efficient and simple uni-directional handshaking scheme emanating from the last stage in the pipeline back towards the remaining stages of the pipeline. This handshaking scheme is extended to handle the join and forks of data flows encountered in non-linear pipelines. A concept design of a four-bit 16-stage pipeline is presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism. The signal timing analysis of this pipeline reveals that the duration of the evaluate and reset phase remains constant in the stages located to the left of the last stage in the pipeline. As a result, the last stage operates as a pulse generator with which the remaining stages of the pipeline synchronize in such a way that neighboring stages operates in opposing phases at each cycle of execution.