DocumentCode
3419278
Title
On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation
Author
Girau, B. ; Tisserand, A.
Author_Institution
Lab. d´´Inf. du Parallelisme, CNRS, Lyon, France
fYear
1996
fDate
12-14 Feb 1996
Firstpage
168
Lastpage
175
Abstract
A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation
Keywords
backpropagation; digital arithmetic; field programmable gate arrays; multilayer perceptrons; parallel architectures; FPGA; backpropagation algorithm; digital hardware; multilayer perceptron backpropagation; online arithmetic-based implementation; reprogrammable hardware implementation; Application software; Arithmetic; Computer networks; Concurrent computing; Field programmable gate arrays; Hardware; Multilayer perceptrons; Neural networks; Neurons; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on
Conference_Location
Lausanne
ISSN
1086-1947
Print_ISBN
0-8186-7373-7
Type
conf
DOI
10.1109/MNNFS.1996.493788
Filename
493788
Link To Document