The optimization and application of DDR controller based on multi-core system

An application to improve the performance of DDR memory controller based on network processor is described in this paper. The DDR memory controller is designed to prefetch instructions to get the address relationship of consecutive instructions in advance. The controller can be able to utilizing the policy of Open Page or bank interleaving while the current instruction is executing. The performance of interfacing Virtex-II FPGA to DDR shows that the DDR memory controller can reduce access latency of DDR memory.