Title :
The optimization and application of DDR controller based on multi-core system
Author :
Hui-Hui Zou ; Pei-Jun Ma ; Jiang-Yi Shi ; Kang Li ; Zhi-Xiong Di
Author_Institution :
Dept. of Microelectron., Xidian Univ., Xi´´an, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
An application to improve the performance of DDR memory controller based on network processor is described in this paper. The DDR memory controller is designed to prefetch instructions to get the address relationship of consecutive instructions in advance. The controller can be able to utilizing the policy of Open Page or bank interleaving while the current instruction is executing. The performance of interfacing Virtex-II FPGA to DDR shows that the DDR memory controller can reduce access latency of DDR memory.
Keywords :
field programmable gate arrays; microprocessor chips; multiprocessing systems; storage management; DDR memory controller; Virtex II FPGA; access latency; bank interleaving; multicore system; network processor; prefetch instructions; Field programmable gate arrays; Memory architecture; Memory management; Optimization; Prefetching; Process control; Timing;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467795
