Evaluation of transient fault susceptibility in microprocessor systems

The paper addresses the problem of evaluating transient fault impact on COTS microprocessor systems. We present the problem of fault effect propagation from low logical to software and application levels. Such an analysis is needed to optimize error detection and correction mechanisms at hardware and software levels. For this purpose we use sophisticated fault injectors. The usefulness of the presented approach was proved in many experiments described in the paper. It may support hardware/software co-design.