JTAG-based bitstream compression for FPGA configuration

Author

Rui Jia ; Fei Wang ; Rui Chen ; Xin-Gang Wang ; Hai-Gang Yang

Author_Institution

Grad. Univ. of Chinese Acad. of Sci., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A novel circuit architecture for configuration bitstream compression based on JTAG is proposed. The circuit decompresses and compresses bitstream while FPGA is configured and performs readback accordingly. The compression and decompression operations are implemented dynamically by a concise hardware architecture within the framework of IEEE standard 1149.1. Run Length Encode/Decode (RLE/D) algorithm is used for compression coding. Using Chartered 0.13um single-poly-8-metal process, the chip size is 0.01 mm².

Keywords

data compression; decoding; field programmable gate arrays; FPGA configuration; IEEE standard; RLE-D algorithm; chartered single-poly-8-metal process; chip size; circuit architecture; circuit compression operations; circuit decompression operations; compression coding; field programmable gate arrays; hardware JTAG-based bitstream compression; hardware architecture; readback; run length encode-decode algorithm; Encoding; Field programmable gate arrays; Hardware; Heuristic algorithms; IEEE standards; Radiation detectors; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467807

Filename

6467807