FPGA based design of the railway´s interlocking equipments

This paper describes the architecture of a safety system of the railway´s interlocking equipment, which has been developed for Czech railways. The system will be used for the railway crossing gate. This system is based on FPGA blocks and has to fulfill the requirements for a fault tolerant system with a fail-safe function. The dual logic and TMR principle are used to increase its dependability. Several self-test and self-diagnostics features are used, such as an LFSR based built-in self-test, the FPGA readback and 1 out of 2 error detection codes. The functional logic uses a majority correction and the FPGA box reprogramming to precede the failure. The reliability analyses, models and reliability characteristics calculations of this system are described. Markov chain models are used for the reliability analyses. The TMR principles for fault tolerant system and the dual-TMR logic have been used in our design and both attempts are compared.