Inductor modeling with layout-dependent effects in 40nm CMOS process

Author

Lourandakis, Errikos ; Nikellis, Konstantinos ; Stefanou, Stefanos ; Bantas, Sotiris

Author_Institution

Helic S.A., Athens, Greece

fYear

2012

fDate

16-18 Jan. 2012

Firstpage

81

Lastpage

84

Abstract

Layout-dependent effects (LDE) as they are encountered in modern semiconductor technology processes are addressed and considered in this work. In particular, their effect on inductor modeling is discussed based on experimental results of devices fabricated and characterized in a 40 nm technology process. The proposed vector based modeling approach is accounting for these effects and its validity is demonstrated by comparison to experimental data. Improved correlation to measured inductor metrics such as inductance L and quality factor Q is demonstrated by considering the layout-dependent effects.

Keywords

CMOS integrated circuits; Q-factor; inductance; inductors; semiconductor device models; CMOS process; LDE; inductance; inductor modeling; layout-dependent effects; quality factor; semiconductor technology; size 40 nm; vector based modeling approach; Couplings; Inductance; Inductors; Integrated circuit modeling; Layout; Metals; Resistance; Inductors; nanotechnology; semiconductor device measurement; semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2012 IEEE 12th Topical Meeting on

Conference_Location

Santa Clara, CA

Print_ISBN

978-1-4577-1317-0

Type

conf

DOI

10.1109/SiRF.2012.6160144

Filename

6160144