DocumentCode :
3419842
Title :
Substrate engineering using Smart CutTM and Smart StackingTM for next-generation advanced LSIs
Author :
Yoshimi, Masato ; Cauchy, X. ; Desbonnets, E. ; Radu, Iuliana ; Maleville, C.
Author_Institution :
Soitec Japan, Tokyo, Japan
fYear :
2012
fDate :
Oct. 29 2012-Nov. 1 2012
Firstpage :
1
Lastpage :
2
Abstract :
Substrate engineering using Smart CutTM and Smart StackingTM for advanced LSIs is overviewed. For digital CMOS applications, planar fully-depleted (FD) SOI structure provides a realistic solution to bridge the technology gap between bulk CMOS and three-dimensional FD structures. Production of planar FD-SOI will be started soon in 28nm technology. RF applications, on the other hand, are the areas where substrate engineering is bringing unique values in performance enhancement with cost efficiency. Adoption of high-resistivity SOI in front-end module (FEM) is rapidly in progress. Meanwhile, bonded SOS has been proven to provide excellent RF performance with its ideal Si crystal-quality and insulating substrate. Smart CutTM is also extending applications in power electronics, photonics, and MEMS applications, with its wide range of flexibility in Si and BOX thicknesses. By combining Smart StackingTM and Smart CutTM, various circuit layers can be bonded onto another circuits, constructing innovative multi-functional 3D devices, such as intelligent image sensors, logic-memory stacked devices, advanced photonics circuits, etc.
Keywords :
CMOS digital integrated circuits; MOSFET; elemental semiconductors; silicon; silicon-on-insulator; three-dimensional integrated circuits; FEM; MEMS application; MOSFET; RF application; RF performance; Si; Smart Cut; Smart Stacking; bonded SOS; bulk CMOS; circuit layer; cost efficiency; crystal-quality; digital CMOS application; front-end module; high-resistivity SOI; insulating substrate; intelligent image sensor; logic-memory stacked device; multifunctional 3D device; next-generation advanced LSI; photonics circuit; planar FD-SOI structure; planar fully-depleted SOI structure; power electronics; substrate engineering; technology gap; three-dimensional FD structure; Bonding; CMOS integrated circuits; Photonics; Radio frequency; Silicon; Stacking; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
Type :
conf
DOI :
10.1109/ICSICT.2012.6467819
Filename :
6467819
Link To Document :
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