Title :
A SIMD/dataflow architecture for a neurocomputer for spike-processing neural networks (NESPINN)
Author :
Jahnke, Axel ; Roth, Ulrich ; Klar, Heinrich
Author_Institution :
Inst. fur Mikroelectronik, Tech. Univ. Berlin, Germany
Abstract :
We present the architecture of a a neurocomputer for the simulation of spike-processing biological neural networks (NESPINN). It consists mainly of a neuron state memory, two connectivity units, a spike-event list, a sector unit and the NESPINN chip with a control unit, and eight PEs with 2 kB local on-chip memory each. In order to increase the performance features such as mixed SIMD/dataflow mode are included. The neurocomputer allows the simulation of up to 512 k neurons with a speed-up of ca. 600 over a Sparc-10. It thus allows tackling difficult low vision problems (e.g. scene segmentation) or simulation of the detailed spike behaviour of large cortical networks
Keywords :
computer vision; data flow computing; image segmentation; neural net architecture; parallel architectures; NESPINN; SIMD/dataflow architecture; connectivity units; large cortical networks; local on-chip memory; low vision problems; neurocomputer; neuron state memory; scene segmentation; sector unit; spike-event list; spike-processing neural networks; Assembly; Biological neural networks; Biological system modeling; Brain modeling; Delay; Layout; Network topology; Neural networks; Neurons; Signal processing;
Conference_Titel :
Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on
Conference_Location :
Lausanne
Print_ISBN :
0-8186-7373-7
DOI :
10.1109/MNNFS.1996.493796