On the testability of analog circuits with directive faults: a rule-based solution and an equation check approach

The construction of directive topology graphs for analog circuits under test (ACUTs) is discussed. Based on node observability and verifiability for directive faults, some basic rules are given which would improve the testability of the network. An overdetermined equation unified checking method (OEUC) is also presented in an effort to check the testability of directive circuits. The method first decomposes the network by finding all diagnosable overdetermined equations (DOEs) of the system equation and then checks their consistency; verifies unitedly, which can divide components into several sets; and adds some new measurement values for the next test turn if necessary. Such iteration is carried out repeatedly until the fault location level is satisfied. The fault location process this method is similar to the troubleshooting approach of a repair technician but in the form of a mathematical expression and can therefore be automated